Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

This is an Open Access article distributed under the terms of the Creative Commons Attribution International License CC-BY 4.0 ( http://creativecommons.org/licenses/by/4.0/ ), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.Peer reviewedFinal Published versio

Low power probabilistic online monitoring of systematic erroneous behaviour

Electronic devices with power-constrained embedded systems are used for a variety of IoT applications, such as geo-monitoring, parking sensors and surveillance, which may tolerate few errors and may not be constrained by a strict error detection latency requirement. In this poster, we propose a novel low power online error monitoring technique that produces an alarm signal when systematic erroneous behaviour has occurred over a pre-defined time interval. A monitoring architecture monitors the signal probabilities of the logic cones concurrently to its normal operation and compares them on-chip against the signature of error-free behaviour. Results on a set of the EPFL'15 benchmarks show an average error coverage of 82.9%% of errors induced by stuck-at faults, with an average area cost of 1.2% and an error detection latency of [0.01, 3.3] milliseconds

Low power probabilistic online monitoring of systematic erroneous behaviour

Electronic devices with power-constrained embedded systems are used for a variety of IoT applications, such as geo-monitoring, parking sensors and surveillance, which may tolerate few errors and may not be constrained by a strict error detection latency requirement. In this poster, we propose a novel low power online error monitoring technique that produces an alarm signal when systematic erroneous behaviour has occurred over a pre-defined time interval. A monitoring architecture monitors the signal probabilities of the logic cones concurrently to its normal operation and compares them on-chip against the signature of error-free behaviour. Results on a set of the EPFL'15 benchmarks show an average error coverage of 82.9%% of errors induced by stuck-at faults, with an average area cost of 1.2% and an error detection latency of [0.01, 3.3] milliseconds

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs

Manufacturing defects that do not affect the functional operation of low power Integrated Circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesised using a 32 nm CMOS technology, the trade-offs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R ≳ 10MΩ(weak bridges) and bridges of R ≲ 10MΩ (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27K and 157K gate equivalents, respectively

DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability (DFT) logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers trade-off flexibility between test-application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase test quality when considering systematic variations. Through SPICE simulations, we show complete recovery of the test quality lost due to PDNs. The proposed method is robust sustaining 80.3% to 98.6% of the achieved test quality under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles

Reliable Power Gating with NBTI Aging Benefits

In this paper, we show that Negative Bias Temperature Instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for power gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test-chip manufactured with a TSMC 65nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower Vth compared to the standard power switching fabric. This can be achieved by either re-designing the STs with the identified Vth value, or applying a proper forward body bias to the available power switching fabrics. Through HSPICE simulations, we show lifetime extension up to 21.4X and average static power reduction up to 16.3% compared to standard ST design approach, without additional area overhead. Finally, we show lifetime extension and several performance-cost trade-offs when a target maximum lifetime is considered

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling(DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI)in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead

Aging Benefits in Nanometer CMOS Designs

This document is the Accepted Manuscript version of the following article: Daniele Rossi, Vasileios Tenentes, Sheng Yang, Saqib Khursheed, and Bashir M. Al-Hashimi, ‘Aging Benefits in Nanometer CMOS Designs’, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64 (3), May 2016. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.n this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.Peer reviewedFinal Accepted Versio

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

In this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead. Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4%

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-power-network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3× and 1.45× the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology